The HiSilicon ZIP accelerator implements the zlib and gzip algorithm. It
uses Hisilicon QM as the interface to the CPU.

This patch provides PCIe driver to the accelerator and registers it to
crypto acomp interface. It also uses sgl as data input/output interface.

Signed-off-by: Zhou Wang <[email protected]>
Signed-off-by: Shiju Jose <[email protected]>
Signed-off-by: Kenneth Lee <[email protected]>
Signed-off-by: Hao Fang <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: John Garry <[email protected]>
Signed-off-by: Herbert Xu <[email protected]>